DDR SDRAM - An walk down the memory lane (1)

 Since PCs were not a household commodity when we were undergraduates, our first introduction to "memory" in the context of a microprocessor based system happened through a typical block diagram in Gaonkar. We just read it as a block essential in the system, and that it does the job of storing data. As I started doing more projects and advanced stuff, the understanding of speed, access times, latencies started coming. Somewhere in that same flow, i learnt about double data rate SDRAMs.

First things first :

So a double data rate (DDR) memory is basically an SDRAM - It is a Synchronous Dynamic Random Access Memory. It is synchronous, means that data reads and writes happen in sync with a clock provided by the system. It is dynamic means the data is stored as charge in capacitors inside integrated circuits. Since capacitors tend to lose charge over a period of time, a periodic refresh is required. It is random access means that one can place any address on the address lines, followed by any other address and the data is accurately accessed and produced on the data lines provided the specified timing relations are adhered to.

In the best case, normal SDRAMs are capable of delivering only one word of data every clock cycle.
DDR is double data rate, which means that for a given clock speed, data can be read/written at twice the rate. 2 words of data can be written/read in a single clock cycle.

For the write mechanism, the controller module provides a clock, (which is not free running) called the DQS and the data is written on the positive as well as the negative edge of DQS. The DQS is called as the strobe in same cases. The write signal needs to be asserted.

For the read operation, the controller issues a read command and after a certain number of clock cycles, (called CAS Latency), the memory puts the data on the data bus. This time, the clock to which the data is synchronised is provided by the memory. The same DQS lines as before are used, but this time, the memory drives those. The DDR memory internally prefetches 2 data words so that it can output data on both edges of the clock.

Part 2