DDR SDRAM - An walk down the memory lane (2)

Part 1 | Part 3

We now look at the various aspects of DDR SDRAM one by one.

Reading or writing data needs to follow a command sequence
The construction of SDRAM is in the form of rows and columns of memory elements. Usually, SDRAMs are divided internally into 2 or 4 'banks' or chunks of memory elements. Hence the way to access data from SDRAM is to specify a bank address, then a row address and the column address.
A specific sequence needs to be carried out when reading from or writing to an SDRAM. JEDEC specifies a set of registers and a set of commands for SDRAM. Separate sets of registers and commands are specified for SDRAM, DDR, DDR2 and DDR3 memories.
Before a row can be accessed inside an SDRAM, an ACTIVE command needs to be issued. This opens a row for data access. It is open for data access till access is closed by a "PRECHARGE" command. Usually, an address line lets you select whether AUTO PRECHARGE is enabled. In case of AUTO PRECHARGE, the access to the row is closed automatically.


Data is read/written on both the edges of the strobe signal
The DDR memory system is a source synchronous interface. This means that the clock signal is transported from the transmitter to the receiver along with the data. This clock is not free running, but only driven during data transfer. The signal is called data strobe or DQS for short. Data is transferred on both the edges of DQS. While defining the specification for DDR, the JEDEC committee decided that the while writing to the memory, the controller must align the DQS to the center of the data eye and while reading from the memory, the memory transmits the DQS edge aligned to the data edge. The design-reuse website has a very nice article on the three most critical decisions regarding the DDR specification from JEDEC.

Reading data in bursts is more efficient
Since an entire row is open for access once activated, and data is prefetched, it is most effeciently read in bursts. The access to SDRAM data always happens in bursts and if one is interested in only 1 or 2 bytes/words, then the rest of the bytes/words are masked using the signal DM or data mask.


Periodic Refresh is required to hold the data
The DDR SDRAM memory controller needs to take care of refreshing the memory every specified time interval by issuing the auto refresh command.

Timing specifications between various commands
Data sheets for SDRAMs usually specify timing requirements for the various operations. For example, minimum time interval between precharge of a row in the same bank  to the activation of another row, or amount of time after which ACTIVE command can be issued after the AUTO-REFRESH command can be issued. Since these timings must be strictly adhered to, to ensure accurate data.