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In this part let us discuss the DDR memory signals. A typical DDR memory has the following pins
Address lines input to memory
The address pins are used to
1. Provide row address
2. Provide column address
3. One pin indicates whether PRECHARGE is applicable to one bank or all banks
4. To carry the opcode during the LOAD MODE REGISTER command.
Bank address input
These have follwing function
1. Select the bank during normal operation
2. To determine whether mode register or extended mode register is selected during LOAD MODE REGISTER command
Clock pins
Clock inout (2 pins : CK and CK#)
The clock is a differential clock. All control signals are sampled on crossing of rising CK edge and falling CK# edge
Clock enable
This input high activates the internal clocks, input buffers and output drivers.
Chip select
This signal is active low in most cases. It acts as an enable for the commands. All commands are masked when this signal is sampled high. *
Control pins
RAS, CAS and WE are the control inputs. These three pins alongwith the CS pin define the command being entered. The DDR data sheets usually specify the definitions of various commands like ACTIVE, PRECHARGE, WRITE, READ etc. as a combination of these signals
Data pins
DQ or data lines
This is usually an 8 bit bus, with either 4 or 8 pins active depending on the data bus width. In 16 bit devices this can be 16 bit wide too. This is a bidirectional bus
DQS or data strobe
A single strobe for every 8 data pins. SO for a 16 bit data bus, 2 bit DQS signal exists. DQS is bi-directional.
Data mask signal
DM is a signal input to memory, with one pin per 8 bits of data. For example, for 16 bit data bus, this signal is 2 bits, one bit corresponding to lower 8 bit of data and the other bit corresponding to higher 8 bit of data. This signal is used as a mask during write operation. If this signal is sampled high, then the data byte is masked.
