DDR SDRAM - An walk down the memory lane (Why?)

In any microprocessor based system, fast memory is a requirement to good system performance. Memories have come a long way from the simple SRAM based structures to DDR2 and now DDR3 SDRAMs. From the perspective of a system designer, I have always wanted to explore and summarise the controller requirements, as the memory used migrates from a simple SDRAM to DDR3. This blog series is just an attempt to explore and understand this.
An extensive web search revealed that there are certain resources available abundantly on the web and certain are entirely missing. (I may probably be not searching the right places too :) ). I observed that DDR, DDR2 and DDR3 almost always referred to the PC/Laptop memory DIMM modules in the webworld jargon. Not many people talk about use of these in embedded applications (the HOW part).  There is material available regarding guidance for the PCB design, termination, etc, but the controller design still seems extremely untalked of in the public forums. It could be related to confidential material, design secrets etc, but my attempt here is to only discuss the concepts for the DDR controller design, the issues faced and the possible direction of solutions, The solutions themselves could probably be patents and design secrets!

The series is targeted to anyone new to DDR and DDR module designs. It could act as a refresher to experienced engineers too. As ever, i should mention that my effort is to always learn, so any comments from experienced people reading this series are most welcome.

The way I have structured the series is as follows
Introduction : This covers the very basics of DDR memories, including the data and control signals, overview of physical signal requirements and overview of board design considerations. I do not mean to keep this section exhaustive, as this would mostly be only a compilation of the existing material. I will be putting pointers and the original text is the best read!

Differences between DDR, DDR2 and DDR3: This section will contain the differences between these memories. I plan to keep this section detailed

DDR memory controller design considerations and issues: This section is most likely to contain my own conclusions and explanation after reading up several things.


Part 1
Part 2
Part 3


References

Memory data sheets, application notes and white papers from memory vendors like Micron